Principal Engineer - FPGA/ASIC Design at Rolls-Royce
About the role
Job Description Job Title: Principal Engineer - FPGA/ASIC Design Working Pattern: Hybrid (3 office days a week) Working location: Reston, VA Rolls-Royce is looking for a Principal Engineer - FPGA/ASIC Design (Field Programmable Gate Arrays / Application Specific Integrated Circuit) Design Specialist to join our growing team. This is an exciting opportunity to work on flagship Rolls-Royce programs and play a vital role in solving some of the most complex and interesting technological challenges …
Interview process at Rolls-Royce
General interview process (this company's specific loop isn't published - reach out if you have insider info).
- Recruiter phone screen - typically 20-40 min
- Technical screen - 1 coding problem or take-home; format varies by company
- Onsite / virtual loop - typically 4-6 rounds over 2-3 weeks; exact split of coding, systems design, and behavioral varies by role and location
Platforms used: unknown — MiPrep tested compatible with major platforms
How to prepare
MiPrep helps you rehearse the specific cadence and question types Rolls-Royce interviewers score on. Upload your resume and this job description; MiPrep generates a rehearsed answer set in your voice from your own projects.