Embedded Systems Interview Questions & Answers (2026)

What is the difference between volatile and const qualifiers in C, and when would you use each in embedded code?

volatile tells the compiler that a variable can change outside the program flow—e.g., hardware registers or ISR‑updated flags—so it must not cache the value in a register. const indicates read‑only data, allowing the compiler to place it in flash and optimize accesses. In embedded code you mark a peripheral register as volatile to ensure each read/write hits the hardware, while marking configuration tables as const to save RAM and enable compiler‑time checks.

volatile uint32_t *TIM_CR = (uint32_t *)0x40000000; const uint8_t lookup[256] = { … };

Explain how a basic timer interrupt works on a microcontroller.

A hardware timer counts clock cycles; when it reaches a preset compare value, it triggers an interrupt request. The CPU saves context, jumps to the ISR, executes user code—often incrementing a tick counter or toggling an LED—and then clears the interrupt flag before returning. Properly configuring prescaler and period determines the interrupt frequency, enabling deterministic timing for tasks like debouncing or periodic sensor sampling.

void TIM2_IRQHandler(void) { tick++; TIM2->SR &= ~TIM_SR_UIF; }

What are the main trade‑offs between polling and interrupt‑driven I/O?

Polling repeatedly checks a peripheral status, consuming CPU cycles even when no data is ready, which can simplify code but wastes power and reduces responsiveness. Interrupt‑driven I/O wakes the CPU only when needed, improving efficiency and latency, but adds complexity: ISR overhead, priority handling, and potential race conditions. Choose polling for low‑rate, non‑critical tasks; use interrupts for time‑sensitive or power‑constrained designs.

How does a watchdog timer improve system reliability?

A watchdog timer (WDT) runs independently of the main CPU and expects periodic resets (kicks) from software. If the software hangs or crashes, the WDT expires and forces a system reset, returning the device to a known state. This mechanism guards against stuck loops, memory corruption, or peripheral deadlocks, providing a simple hardware‑level fault recovery without requiring external monitoring.

Describe the purpose of a linker script in embedded development.

A linker script defines how sections of compiled code and data are placed in the target memory map. It assigns flash for .text, RAM for .data and .bstack, and can reserve regions for interrupt vectors or peripheral registers. Precise control prevents overlap, ensures bootloader compatibility, and allows placement of critical routines in fast memory, which is essential for deterministic performance on constrained devices.

What is priority inversion and how can it be mitigated in an RTOS?

Priority inversion occurs when a low‑priority task holds a resource needed by a high‑priority task, while a medium‑priority task preempts the low‑priority one, blocking the high‑priority task. RTOSes mitigate this with priority inheritance: the low‑priority task temporarily inherits the higher priority until it releases the resource, ensuring the medium task cannot preempt it and the high‑priority task resumes promptly.

Explain the difference between a binary semaphore and a mutex in an RTOS.

Both synchronize tasks, but a binary semaphore has no ownership concept; any task can give or take it, making it suitable for signaling events. A mutex includes priority inheritance and ownership, preventing priority inversion when protecting shared resources. Use a mutex for mutual exclusion of critical sections, and a binary semaphore for simple task-to-task notifications.

How would you implement a thread‑safe circular buffer for UART reception?

Allocate a fixed‑size array with head and tail indices. In the UART ISR, write incoming bytes to the buffer, advance head, and handle overflow by discarding oldest data or signaling an error. In the consumer task, read from tail, advance tail, and use atomic operations or disable interrupts briefly to protect index updates. This design decouples ISR timing from processing latency.

volatile uint8_t rx_buf[128]; volatile uint8_t head, tail; void UART_ISR(void){ rx_buf[head++] = UART->RDR; if(head==sizeof(rx_buf)) head=0; }

What are the advantages of using DMA for ADC data acquisition?

DMA transfers ADC conversion results directly to memory without CPU intervention, freeing the core for other tasks and reducing jitter. It enables high‑throughput sampling, consistent timing, and lower power consumption because the CPU can sleep between bursts. Additionally, DMA can chain multiple transfers, allowing continuous streaming of data for signal processing pipelines.

Describe how you would debug a hard‑fault on an ARM Cortex‑M processor.

First, enable the HardFault handler to capture the stack frame and read the HFSR, CFSR, and BFAR registers. Use a debugger to inspect the program counter (PC) at the fault, then backtrack to the offending instruction. Check for unaligned accesses, null pointer dereferences, or illegal privilege escalations. If the fault persists, add sentinel registers or use a watchdog to capture state before reset.

Explain the concept of memory‑mapped I/O and its implications for compiler optimizations.

Memory‑mapped I/O treats peripheral registers as ordinary addresses, allowing reads/writes via normal load/store instructions. However, because accesses have side effects, the compiler must not reorder, cache, or eliminate them. Declaring registers as volatile prevents such optimizations, ensuring each access occurs exactly as coded, which is critical for correct peripheral control and timing.

How does a real‑time operating system achieve deterministic task scheduling?

An RTOS uses a fixed‑priority preemptive scheduler or a time‑slice round‑robin approach with known worst‑case execution times. By guaranteeing that higher‑priority tasks can preempt lower‑priority ones and that context switches have bounded latency, the system can provide predictable response times. Configurable tick rates and priority inheritance further tighten determinism for shared resources.

What is the purpose of a bootloader in embedded devices?

A bootloader initializes hardware, verifies firmware integrity, and loads the main application into execution. It enables in‑field firmware updates via UART, USB, or OTA, providing a recovery path if the application crashes. By residing in a protected flash region, it can also enforce security checks like digital signatures before handing control to the new image.

Compare static linking versus dynamic linking for firmware updates.

Static linking incorporates all libraries into the firmware binary, yielding a single monolithic image that simplifies deployment and reduces runtime overhead—ideal for constrained devices. Dynamic linking allows swapping modules without reflashing the entire image, facilitating modular updates and memory savings, but introduces runtime relocation, versioning complexity, and potential security risks. Choose static linking for safety‑critical, low‑memory designs; dynamic linking when modularity outweighs overhead.

Explain how you would design a low‑power sleep strategy for a battery‑operated sensor node.

Identify the deepest low‑power mode the MCU supports (e.g., STOP or STANDBY) and configure peripheral clocks to shut down. Use an RTC or external interrupt to wake the device at required intervals, keep only essential RAM retained, and place the sensor in its own low‑power state. Ensure the wake‑up sequence restores clocks and reinitializes peripherals, then quickly acquire data and return to sleep to maximize battery life.

What are the security considerations when implementing OTA firmware updates?

Secure OTA must verify authenticity and integrity of the new image using cryptographic signatures (e.g., ECDSA). Store the update in a separate flash bank, perform a hash check before swapping, and protect the bootloader from tampering. Use encrypted transport (TLS) to prevent man‑in‑the‑middle attacks, and implement rollback protection to avoid downgrading to vulnerable versions.

Describe the impact of cache coherency on multi‑core embedded systems.

Cache coherency ensures that multiple cores see a consistent view of shared memory. Without it, one core may read stale data while another has updated it, leading to race conditions. Hardware coherency protocols (MESI) or software mechanisms (memory barriers, lock primitives) must be employed. In safety‑critical designs, disabling caches or using lock‑free algorithms can simplify reasoning at the cost of performance.

How would you mitigate electromagnetic interference (EMI) in a high‑speed PCB layout?

Route high‑speed traces as short, straight lines with controlled impedance, keep them away from sensitive analog sections, and use ground planes to provide return paths. Add decoupling capacitors near power pins, employ differential pairs for signals like USB or Ethernet, and use proper via stitching. Shield critical components and follow spacing rules for trace separation to reduce radiated emissions.

Explain the difference between hard real‑time and soft real‑time constraints.

Hard real‑time systems must meet deadlines absolutely; a missed deadline can cause catastrophic failure (e.g., automotive brakes). Soft real‑time systems tolerate occasional deadline misses with degraded performance (e.g., multimedia playback). Design choices—such as deterministic scheduling, priority levels, and buffer sizing—reflect the required guarantee level, with hard real‑time demanding stricter resource allocation and verification.

What is a memory protection unit (MPU) and how does it improve safety in embedded firmware?

An MPU defines regions with access permissions (read/write/execute) and can enforce privilege levels. By isolating critical code and data, it prevents errant pointers or malicious code from corrupting system memory, reducing the risk of crashes or security breaches. Configuring the MPU during startup and validating region boundaries is a common practice in safety‑critical standards like IEC 61508.

How does a CAN bus arbitration mechanism ensure deterministic message transmission?

CAN uses a non‑destructive bitwise arbitration where each node transmits its identifier concurrently. Dominant bits (0) override recessive bits (1). The node with the lowest identifier (most dominant) wins the bus without collision, while others stop transmitting and retry later. This deterministic priority scheme guarantees that high‑priority messages get through even under heavy load.