Senior ASIC Frontend Engineer - RTL & SystemVerilog (Northern) at Upscale AI, Inc.
About the role
Upscale AI, Inc. is seeking a seasoned ASIC Design engineer to define micro-architecture for next-generation designs and own RTL entry that meets power, performance, and area targets. You will collaborate with architecture, verification, emulation, and physical design teams to validate test plans, closures, and DFT integration in a fast-paced startup environment. Ideal candidates have SystemVerilog expertise, 3 years of ASIC logic design, and strong teamwork capabilities to help drive J-18808-L…
Interview process at Upscale AI, Inc.
General interview process (this company's specific loop isn't published - reach out if you have insider info).
- Recruiter phone screen - typically 20-40 min
- Technical screen - 1 coding problem or take-home; format varies by company
- Onsite / virtual loop - typically 4-6 rounds over 2-3 weeks; exact split of coding, systems design, and behavioral varies by role and location
Platforms used: unknown — MiPrep tested compatible with major platforms
How to prepare
MiPrep helps you rehearse the specific cadence and question types Upscale AI, Inc. interviewers score on. Upload your resume and this job description; MiPrep generates a rehearsed answer set in your voice from your own projects.